Boahen, Kwabena A

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2000 - 200725
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  • Publication
    Optic Nerve Signals in a Neuromorphic Chip II: Testing and Results
    (2004-04-01) Zaghloul, Kareem A.; Boahen, Kwabena A
    Seeking to match the brain’s computational efficiency [14], we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 μm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip’s subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip’s circuit design is described in a companion paper [Zaghloul and Boahen (2004)].
  • Publication
    On-off differential current-mode circuits for Gabor-type spatial filtering
    (2002-05-26) Shi, Bertram E.; Choi, Thomas Yu Wing; Boahen, Kwabena A
    We describe a current-mode circuit for Gabor-type image filtering which uses a differential representation where positive (on) and negative (off) signals are encoded using separate channels. Previous current-mode implementations represented positive and negative signals as variations around a constant bias at every pixel. However, this bias current has several disadvantages. First, variations in it introduce significant additive fixed pattern noise to the output. Second, it dissipates power even with zero input. Third, if the output is encoded using the Address Event Representation, the bias current sets up a quiescent firing rate which loads the bus. The architecture proposed here alleviates these problems since a zero signal is encoded as nearly zero current in both channels. On the other hand, the transistor count and the address space are doubled. Measurements from a 1 by 25 pixel array with a cell size of 64 μm by 540 μm was fabricated in the AMI 1.5 μm process available through MOSIS. Quiescent power dissipation was 5 μW total.
  • Publication
    Thermodynamically Equivalent Silicon Models of Voltage-Dependent Ion Channels
    (2007-01-01) Hynna, Kai M; Boahen, Kwabena A
    We model ion channels in silicon by exploiting similarities between the thermodynamic principles that govern ion channels and those that govern transistors. Using just eight transistors, we replicate—for the first time in silicon—the sigmoidal voltage dependence of activation (or inactivation) and the bell-shaped voltage-dependence of its time constant. We derive equations describing the dynamics of our silicon analog and explore its flexibility by varying various parameters. In addition, we validate the design by implementing a channel with a single activation variable. The design’s compactness allows tens of thousands of copies to be built on a single chip, facilitating the study of biologically realistic models of neural computation at the network level in silicon.
  • Publication
    A silicon implementation of the thalamic low threshold calcium current
    (2003-09-17) Hynna, Kai M.; Boahen, Kwabena A
    A silicon model of the thalamic low threshold calcium current is presented. The channel current (IT) is the product of an activation and inactivation current, normalized by their sum. The individual currents are modeled by a simple current-mirror integrator circuit. A modified differential pair controls the threshold of activation while a leak transistor added to the inactivation mirror controls the rate of inactivation and deinactivation. The dynamics of IT are the result of the interaction between the fast activation and slow inactivation currents. By adjusting the base level of the activation current, we can realize a hyperpolarization activated cation current (Ih), responsible for rhythmic bursting in thalamic cells. By attaching the circuit to a constant leak integrate-and-fire neuron, we demonstrate in silicon both burst and tonic firing modes.
  • Publication
    A biomorphic digital image sensor
    (2003-02-01) Culurciello, Eugenio; Etienne-Cummings, Ralph; Boahen, Kwabena A
    An arbitrated address-event imager has been designed and fabricated in a 0.6-μm CMOS process. The imager is composed of 80 x 60 pixels of 32 x 30 μm. The value of the light intensity collected by each photosensitive element is inversely proportional to the pixel’s interspike time interval. The readout of each spike is initiated by the individual pixel; therefore, the available output bandwidth is allocated according to pixel output demand. This encoding of light intensities favors brighter pixels, equalizes the number of integrated photons across light intensity, and minimizes power consumption. Tests conducted on the imager showed a large output dynamic range of 180 dB (under bright local illumination) for an individual pixel. The array, on the other hand, produced a dynamic range of 120 dB (under uniform bright illumination and when no lower bound was placed on the update rate per pixel). The dynamic range is 48.9 dB value at 30-pixel updates/s. Power consumption is 3.4 mW in uniform indoor light and a mean event rate of 200 kHz, which updates each pixel 41.6 times per second. The imager is capable of updating each pixel 8.3K times per second (under bright local illumination).
  • Publication
    A multi-chip implementation of cortical orientation hypercolumns
    (2004-05-23) Choi, Thomas Y. W.; Shi, Bertram E.; Boahen, Kwabena A
    This paper describes a neuromorphic implementation of the orientation hypercolumns found in the mammalian primary visual cortex. A hypercolumn contains a group of neurons that respond to the same retinal location, but with different orientation preferences. The system consists of a single silicon retina feeding multiple orientation selective chips, each of which contains neurons tuned to the same orientation, but with different receptive field centers and spatial phases. All chips operate in continuous time, and communicate with each other using spikes transmitted by the asynchronous digital Address Event Representation communication protocol. This enables us to implement recurrent interactions between neurons within one hypercolumn, even though they are located on different chips. We demonstrate this by measuring shifts in orientation selectivity due to changes in the feedback.
  • Publication
    A linear cochlear model with active bi-directional coupling
    (2003-09-17) Wen, Bo; Boahen, Kwabena A
    We present a linear active cochlear model that includes the outer hair cell (OHC) forces, which are delivered onto upstream and downstream basilar membrane (BM) segments through Deiters' cells (DCs) and their phalangeal processes (PhPs). Due to the longitudinal tilt of the OHC towards the base and the oblique orientation of the PhP towards the apex, each BM segment receives both feed-forward and feed-backward OHC forces. Transverse BM fibers are actively coupled longitudinally through these bi-directional OHC forces, included in a cochlear model for the first time. We present simulation results that demonstrate large amplification and sharp tuning, and we analyze the underlying mechanism.
  • Publication
    Arbitrated address event representation digital image sensor
    (2001-02-05) Culurciello, Eugenio; Etienne-Cummings, Ralph; Boahen, Kwabena A
    80×60 (1/8 VGA) address event imager in 0.6 μm CMOS converts light intensity into a one-bit code (a spike). The read-out of each spike is initiated by the pixel. The dynamic range is 200 dB for a pixel and 120 dB for the array. It uses 3.4 mW at a spike rate of 200 kHz. It is capable of 8.3 k effective frames/s.
  • Publication
    Recurrently Connected Silicon Neurons with Active Dendrites for One-Shot Learning
    (2004-07-25) Arthur, John V.; Boahen, Kwabena A
    We describe a neuromorphic chip designed to model active dendrites, recurrent connectivity, and plastic synapses to support one-shot learning. Specifically, it is designed to capture neural firing patterns (short-term memory), memorize individual patterns (long-term memory), and retrive them when primed (associative recall). It consists of a recurrently connected population of excitatory pyramidal cells and a recurrently connected population of inhibitory basket cells. In addition to their recurrent connections, the excitatory and inhibitory populations are reciprocally connected. The model is novel in that it utilizes recurrent connections and active dendrites to maintain short-term memories as well as to store long-term memories.
  • Publication
    Point-to-point connectivity between neuromorphic chips using address events
    (2000-05-01) Boahen, Kwabena A
    This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log2 (N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles--spikes clustered in space and in time. This paper quantifies tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice.The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to √N) by organizing neurons into rows and columns, and reduced in time (from log2 (N) to 2) by exploiting locality in the arbiter tree and in the row–column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog–digital systems are described.