A burst-mode word-serial address-event link--III: analysis and test results
fair arbiter design
We present results for a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS. Capacity scales with integration density because an entire row is read and written in parallel. Row activity is encoded in a burst: The row address followed by a column address for each active cell. We predict the distribution of burst lengths when transmission is initiated by active cells and access is arbitered using a two-level queuing model. Agreement with the experiment is excellent for loads over 50% but not for lighter loads, where our assumption that service time is exponentially distributed breaks down. We also quantify the throughput–latency tradeoff. The price of an n-fold increase in throughput is an n per Ncol timing error in a cell’s inter-event interval, where Ncol is the number of cells per row. Links implemented in 0.6, 0.4, and 0.25 micrometer are compared; the highest burst-rate achieved was 27.8 M events/s.