Departmental Papers (ESE)


An architectural overview of an image sensor with general spatial processing capabilities on the focal plane is presented. The system has been fabricated on two separate tiers, implemented on silicon-on-insulator technology with vertical interconnect capabilities. One tier is dedicated to imaging, where photosensitivity and pixel fill have been optimized. The subsequent layers contain noise suppression and digitally controlled analog processing elements, where general spatial filtering is computed. The digitally controlled aspect of the processing unit allows generic receptive fields to be computed on read out. The image is convolved with four receptive fields in parallel. The chip provides parallel readout of the filtered results and the intensity image.

Document Type

Conference Paper

Date of this Version

May 2006


Copyright 2006 IEEE. Reprinted from Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006), May 2006, pages 4963-4966.

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to By choosing to view this document, you agree to all provisions of the copyright laws protecting it.


3-D technology, focal plane imager



Date Posted: 27 June 2007

This document has been peer reviewed.