Van der Spiegel, Jan

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Disciplines
Electrical and Electronics
Research Projects
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Position
Professor of Electrical Science and Engineering
Introduction
Research Interests Vision Sensors: We are studying novel current-mode image sensors with analog spatial processing and a new pixel array design, in which several techniques are combined to improve the quality of the images. Included in the design is a new addressing scheme that allows a group of pixels to share the same readout circuitry, therefore reducing the pixel size and increasing the resolution. The new design has removed the in-pixel accessing switches, and uses velocity saturated operation in order to increase the readout linearity. We are also integrating a successive approximation ADC on the imager. The ADC is natively current mode, and is designed to interface directly with the current mode pixels without the need for sample-and-hold circuits or current-to-voltage converters. Sensor for Polarization Imaging: We are also developing a focal plane imaging sensor capable of real time extraction of polarization information. The imaging system consists of a photo array of linear current mode active pixel sensors and analog processing circuitry for computation of the Stokes parameters. A dual-tier thin film micro-polarizer array has been deposited on the imager. A commercially available thin film polarizer is used to create an array of micro-polarizers. The thin film polarizer consists of an iodine-doped Polyvinyl Alcohol (PVA) layer which is patterned and etched using RIE. The measured extinction ratios of the filters are 1000 and 100 for the blue/green and red spectrum, respectively. Mixed mode Integrated Circuits for Data Acquisition Systems and Communications: We are currently exploring different architectures and algorithms to realize high performance analog-to-digital converters. One project deals background calibration schemes to correct for any residual non-idealities (linear and non-linear) in pipe-lined analog-to-digital converters. We are also developing CMOS circuits for RF communications using AlN Contour-Mode Piezoelectric Resonators in collaboration with Prof. G. Lucca’s group.
Research Interests

Search Results

Now showing 1 - 10 of 47
  • Publication
    Multi-Frequency Pierce Oscillators Based On Piezoelectric AlN Contour-Mode MEMS Resonators
    (2008-09-01) Zuo, Chengjie; Sinha, Nipun; Van der Spiegel, Jan; Piazza, Gianluca
    This paper reports on the first demonstration of multi-frequency (176, 222, 307, and 482 MHz) oscillators based on piezoelectric AlN contour-mode MEMS resonators. All the oscillators show phase noise values between –88 and –68 dBc/Hz at 1 kHz offset and phase noise floors as low as –160 dBc/Hz at 1 MHz offset. The same Pierce circuit design is employed to sustain oscillations at the 4 different frequencies, while the oscillator core consumes at most 10 mW. The AlN resonators are currently wirebonded to the integrated circuit realized in the AMIS 0.5 μm 5 V CMOS process. This work constitutes a substantial step forward towards the demonstration of a single-chip multi-frequency reconfigurable timing solution that could be used in wireless communications and sensing applications.
  • Publication
    GBOPCAD: A Synthesis Tool for High-Performance Gain-Boosted Opamp Design
    (2005-08-01) Yuan, Jie; Farhat, Nabil H; Van der Spiegel, Jan
    A systematic design methodology for high-performance gain-boosted opamps (GBOs) is presented. The methodology allows the optimization of the GBO in terms of ac response and settling performance and is incorporated into an automatic computer-aided design (CAD) tool, called GBOPCAD. Analytic equations and heuristics are first used by GBOPCAD to obtain a sizing solution close to the global optimum. Then, simulated annealings are used by GBOPCAD to find the global optimum. A sample opamp is designed by this tool in a 0.6-μm CMOS process. It achieves a dc gain of 80 dB, a unity-gain bandwidth of 836 MHz with 60o phase margin and a 0.0244% settling time of 5 ns. The sample/hold front-end of a 12-bit 50-MSample/s analog–digital converter was implemented with this opamp. It achieves a signal-to-noise ratio of 81.9 dB for a 8.1-MHz input signal.
  • Publication
    Analysis of Clock Buffer Phase Noise
    (2002-05-26) Xu, Chao; Laker, Kenneth R; Barber, Frank; Van der Spiegel, Jan
    This paper presents a phase noise model for clock buffers. The model can be used to predict the phase noise introduced by clock buffers and to gain insight into phase noise transfer mechanisms in clock buffers. Based on the models, techniques for low phase noise clock buffer design are derived. The analytical results presented here have good agreement with simulation and measurement results.
  • Publication
    Acoustic-Phonetic Features for the Automatic Classification of Stop Consonants
    (2001-11-01) Ali, Ahmed M. Abdelatty; Van der Spiegel, Jan; Mueller, Paul
    In this paper, the acoustic–phonetic characteristics of American English stop consonants are investigated. Features studied in the literature are evaluated for their information content and new features are proposed. A statistically guided, knowledge-based, acoustic–phonetic system for the automatic classification of stops, in speaker independent continuous speech, is proposed. The system uses a new auditory-based front-end processing and incorporates new algorithms for the extraction and manipulation of the acoustic–phonetic features that proved to be rich in their information content. Recognition experiments are performed using hard decision algorithms on stops extracted from the TIMIT database continuous speech of 60 speakers (not used in the design process) from seven different dialects of American English. An accuracy of 96% is obtained for voicing detection, 90% for place articulation detection and 86% for the overall classification of stops.
  • Publication
    Cort-X II: Low Power Element Design of a Large-Scale Spatio-Temporaral Pattern Clustering System
    (2007-05-01) Yuan, Jie; Farhat, Nabil H; Song, Ning; Van der Spiegel, Jan
    Complex spatio-temporal patterns can be clustered using a network of parametrically coupled logistic maps. This paper describes the processing element design of such a Cort-X system. Each Cort-X element consists of a non-linear coupling (LC) and a non-linear dynamic element (IRON). The circuits are designed for low-power operation and to be robust against process variations. This has been accomplished by using openloop circuits, and a self-calibration technique that compensate for process variations. The circuits were implemented in a 0.25 um, 2.5V CMOS process and consumes a total of 12mW of power at 1MHz which is about a factor of 20 less power than previous realizations. This opens the possibility for building a large-scale Cort-X system on a chip for the recognition of complex spatio-temporal patterns.
  • Publication
    Image Sensor with General Spatial Processing in a 3D Integrated Circuit Technology
    (2006-05-01) Gruev, Viktor; Van der Spiegel, Jan; Philipp, Ralf M.; Etienne-Cummings, Ralph
    An architectural overview of an image sensor with general spatial processing capabilities on the focal plane is presented. The system has been fabricated on two separate tiers, implemented on silicon-on-insulator technology with vertical interconnect capabilities. One tier is dedicated to imaging, where photosensitivity and pixel fill have been optimized. The subsequent layers contain noise suppression and digitally controlled analog processing elements, where general spatial filtering is computed. The digitally controlled aspect of the processing unit allows generic receptive fields to be computed on read out. The image is convolved with four receptive fields in parallel. The chip provides parallel readout of the filtered results and the intensity image.
  • Publication
    1.05-GHz CMOS Oscillator Based on Lateral-Field-Excited Piezoelectric AlN Contour-Mode MEMS Resonators
    (2010-01-01) Zuo, Chengjie; Van der Spiegel, Jan; Piazza, Gianluca
    This paper reports on the first demonstration of a 1.05-GHz microelectromechanical (MEMS) oscillator based on lateral-field-excited (LFE) piezoelectric AlN contour-mode resonators. The oscillator shows a phase noise level of −81 dBc/Hz at 1-kHz offset frequency and a phase noise floor of −146 dBc/Hz, which satisfies the global system for mobile communications (GSM) requirements for ultra-high frequency (UHF) local oscillators (LO). The circuit was fabricated in the AMI semiconductor (AMIS) 0.5-μm complementary metal-oxide-semiconductor (CMOS) process, with the oscillator core consuming only 3.5 mW DC power. The device overall performance has the best figure-of-merit (FoM) when compared with other gigahertz oscillators that are based on film bulk acoustic resonator (FBAR), surface acoustic wave (SAW), and CMOS on-chip inductor and capacitor (CMOS LC) technologies. A simple 2-mask process was used to fabricate the LFE AlN resonators operating between 843 MHz and 1.64 GHz with simultaneously high Q (up to 2,200) and kt2 (up to 1.2%). This process further relaxes manufacturing tolerances and improves yield. All these advantages make these devices suitable for post-CMOS integrated on-chip direct gigahertz frequency synthesis in reconfigurable multiband wireless communications.
  • Publication
    A CMOS Monolithic Implementation of a Nonlinear Element for Arbitrary 1-D Map Generation
    (2006-05-01) Farhat, Nabil H; Yuan, Jie; Van der Spiegel, Jan
    In a macroscopic approach, a single-chip cortical patch is designed based on a the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabrication in a 0.6um CMOS process, and it driven under signals with 1MHz frequency. It covers a die of 0.2 square mm, and consumes 40mW power, with a 5V supply.
  • Publication
    Robust Auditory-Based Speech Processing Using the Average Localized Synchrony Detection
    (2002-07-01) Ali, Ahmed M. Abdellaty; Van der Spiegel, Jan; Mueller, Paul
    In this paper, a new auditory-based speech processing system based on the biologically rooted property of the average localized synchrony detection (ALSD) is proposed. The system detects periodicity in the speech signal at Bark-scaled frequencies while reducing the response’s spurious peaks and sensitivity to implementation mismatches, and hence presents a consistent and robust representation of the formants. The system is evaluated for its formant extraction ability while reducing spurious peaks. It is compared with other auditory-based and traditional systems in the tasks of vowel and consonant recognition on clean speech from the TIMIT database and in the presence of noise. The results illustrate the advantage of the ALSD system in extracting the formants and reducing the spurious peaks. They also indicate the superiority of the synchrony measures over the mean-rate in the presence of noise.
  • Publication
    A CMOS Monolithic Implementation of a Nonliniear Interconnection Module for a Corticonic Network
    (2006-05-01) Farhat, Nabil H; Yuan, Jie; Van der Spiegel, Jan
    A nonlinear interconnection module for a corticonic network is designed and fabricated in a 0.6µm CMOS process. The module uses NMOS transistors in weak-inversion for nonlinearity. A calibration scheme is developed to compensate for the process and temperature variations of the circuit. The designed module has an area of 0.35 sq. mm2. It consumes 200mW of power, with 5V power supply. Simulation results show that the circuit is able to implement the target parametric coupling function accurately.