Departmental Papers (ESE)


A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency.

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Conference Paper

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Copyright 2001 IEEE. Reprinted from Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems 2001 (ICECS 2001) Volume 1, pages 55-58.
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Date Posted: 09 November 2004

This document has been peer reviewed.