Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter
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Departmental Papers (ESE)
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Electrical and Computer Engineering
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A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency.
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2001-09-02
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2023-05-16T21:40:17.000
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Copyright 2001 IEEE. Reprinted from Proceedings of the 8th IEEE International Conference on Electronics, Circuits and Systems 2001 (ICECS 2001) Volume 1, pages 55-58. Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=20704 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.