Sargeant, Winslow

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  • Publication
    Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and +-35ps Jitter
    (2001-09-02) Sargeant, Winslow; Laker, Kenneth R; Xu, Chao; Van der Spiegel, Jan
    A fully integrated phase-locked loop (PLL) fabricated in a 0.24 micrometer, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chip. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24 micrometer CMOS technology. Also it has very low peak-to-peak jitter less than +-35ps at 1.25GHz output frequency.