Departmental Papers (ESE)


This paper presents a phase noise model for clock buffers. The model can be used to predict the phase noise introduced by clock buffers and to gain insight into phase noise transfer mechanisms in clock buffers. Based on the models, techniques for low phase noise clock buffer design are derived. The analytical results presented here have good agreement with simulation and measurement results.

Document Type

Conference Paper

Date of this Version

May 2002


Copyright 2002 IEEE. Reprinted from Proceedings of the 2002 IEEE International Symposium on Circuits and Systems (ISCAS 2002), Volume 5, pages 657-660.
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Date Posted: 24 November 2004

This document has been peer reviewed.