Departmental Papers (ESE)
Abstract
In a macroscopic approach, a single-chip cortical patch is designed based on a the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabrication in a 0.6um CMOS process, and it driven under signals with 1MHz frequency. It covers a die of 0.2 square mm, and consumes 40mW power, with a 5V supply.
Document Type
Conference Paper
Date of this Version
May 2006
Keywords
cortical patch, bifurcating neuron, nonlinear element, one-dimensional logistic map
Date Posted: 27 June 2007
This document has been peer reviewed.
Comments
Copyright 2006 IEEE. Reprinted from Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006), May 2006, pages 2765-2768.
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