A CMOS Monolithic Implementation of a Nonlinear Element for Arbitrary 1-D Map Generation
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Departmental Papers (ESE)
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cortical patch
bifurcating neuron
nonlinear element
one-dimensional logistic map
bifurcating neuron
nonlinear element
one-dimensional logistic map
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In a macroscopic approach, a single-chip cortical patch is designed based on a the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabrication in a 0.6um CMOS process, and it driven under signals with 1MHz frequency. It covers a die of 0.2 square mm, and consumes 40mW power, with a 5V supply.
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2006-05-01
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Departmental Papers (ESE)
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2023-05-17T00:51:16.000
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Copyright 2006 IEEE. Reprinted from Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006), May 2006, pages 2765-2768. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.