Analysis of Clock Buffer Phase Noise
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This paper presents a phase noise model for clock buffers. The model can be used to predict the phase noise introduced by clock buffers and to gain insight into phase noise transfer mechanisms in clock buffers. Based on the models, techniques for low phase noise clock buffer design are derived. The analytical results presented here have good agreement with simulation and measurement results.
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Copyright 2002 IEEE. Reprinted from Proceedings of the 2002 IEEE International Symposium on Circuits and Systems (ISCAS 2002), Volume 5, pages 657-660. Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=21767&page=11 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.