A 1.2 V, 38 microW Second-Order DeltaSigma Modulator with Signal Adaptive Control Architecture
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Departmental Papers (ESE)
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delta-sigma converter
modulator
oversampling
adaptive architecture
modulator
oversampling
adaptive architecture
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A 1.2 V, 38 μW second-order ΔΣ modulator (ΔΣM) with a Signal Adaptive Control (SAC) architecture is fabricated in a 0.35 μm standard CMOS technology (Vt,n = 0.6V, Vt,p = -0.8V). This modulator achieves 75 dB dynamic range and 63 dB of peak SNDR at 6.8kHz Nyquist rate and an oversample ratio of 64. The proposed architecture effectively reduces the power dissipation while keeping the modulator performance almost unchanged.
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2001-03-26
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Departmental Papers (ESE)
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2023-05-16T22:03:55.000
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Copyright 2001 IEEE. Reprinted from Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits and Systems 2001 (DCAS 2001), pages P23-P26. Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=19922 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.