Departmental Papers (BE)

Document Type

Journal Article

Date of this Version

February 2004


This paper describes the electronic implementation of a four-layer cellular neural network architecture implementing two components of a functional model of neurons in the visual cortex: linear orientation selective filtering and half wave rectification. Separate ON and OFF layers represent the positive and negative outputs of two-phase quadrature Gabor-type filters, whose orientation and spatial-frequency tunings are electronically adjustable. To enable the construction of a multichip network to extract different orientations in parallel, the chip includes an address event representation (AER) transceiver that accepts and produces two-dimensional images that are rate encoded as spike trains. It also includes routing circuitry that facilitates point-to-point signal fan in and fan out. We present measured results from a 32 x 64 pixel prototype, which was fabricated in the TSMC0.25-μm process on a 3.84 by 2.54 mm die. Quiescent power dissipation is 3 mW and is determined primarily by the spike activity on the AER bus. Settling times are on the order of a few milliseconds. In comparison with a two-layer network implementing the same filters, this network results in a more symmetric circuit design with lower quiescent power dissipation, albeit at the expense of twice as many transistors.


Copyright 2004 IEEE. Reprinted from IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 51, Issue 2, February 2004, pages 342-353.
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address event representation (AER), analog circuits, asynchronous logic, Gabor filter, image processing, neuromorphic engineering, nonlinear circuits, visual cortex



Date Posted: 10 November 2004

This document has been peer reviewed.