An ON-OFF orientation selective address event representation image transceiver chip

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dc.contributor.authorChoi, Thomas Yu Wing
dc.contributor.authorShi, Bertram E.
dc.contributor.authorBoahen, Kwabena A
dc.date2023-05-16T21:41:01.000
dc.date.accessioned2023-05-22T12:08:42Z
dc.date.available2023-05-22T12:08:42Z
dc.date.issued2004-02-01
dc.date.submitted2004-11-10T07:43:55-08:00
dc.description.abstractThis paper describes the electronic implementation of a four-layer cellular neural network architecture implementing two components of a functional model of neurons in the visual cortex: linear orientation selective filtering and half wave rectification. Separate ON and OFF layers represent the positive and negative outputs of two-phase quadrature Gabor-type filters, whose orientation and spatial-frequency tunings are electronically adjustable. To enable the construction of a multichip network to extract different orientations in parallel, the chip includes an address event representation (AER) transceiver that accepts and produces two-dimensional images that are rate encoded as spike trains. It also includes routing circuitry that facilitates point-to-point signal fan in and fan out. We present measured results from a 32 x 64 pixel prototype, which was fabricated in the TSMC0.25-μm process on a 3.84 by 2.54 mm die. Quiescent power dissipation is 3 mW and is determined primarily by the spike activity on the AER bus. Settling times are on the order of a few milliseconds. In comparison with a two-layer network implementing the same filters, this network results in a more symmetric circuit design with lower quiescent power dissipation, albeit at the expense of twice as many transistors.
dc.description.commentsCopyright 2004 IEEE. Reprinted from IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 51, Issue 2, February 2004, pages 342-353. Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=28337&puNumber=8919 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
dc.identifier.urihttps://repository.upenn.edu/handle/20.500.14332/2830
dc.legacy.articleid1019
dc.legacy.fulltexturlhttps://repository.upenn.edu/cgi/viewcontent.cgi?article=1019&context=be_papers&unstamped=1
dc.source.issue16
dc.source.journalDepartmental Papers (BE)
dc.source.peerreviewedtrue
dc.source.statuspublished
dc.subject.otheraddress event representation (AER)
dc.subject.otheranalog circuits
dc.subject.otherasynchronous logic
dc.subject.otherGabor filter
dc.subject.otherimage processing
dc.subject.otherneuromorphic engineering
dc.subject.othernonlinear circuits
dc.subject.othervisual cortex
dc.titleAn ON-OFF orientation selective address event representation image transceiver chip
dc.typeArticle
digcom.identifierbe_papers/16
digcom.identifier.contextkey32320
digcom.identifier.submissionpathbe_papers/16
digcom.typearticle
dspace.entity.typePublication
relation.isAuthorOfPublication93e1cefd-0e80-4a17-92e2-4fc25cb0e18a
relation.isAuthorOfPublication93e1cefd-0e80-4a17-92e2-4fc25cb0e18a
relation.isAuthorOfPublication.latestForDiscovery93e1cefd-0e80-4a17-92e2-4fc25cb0e18a
upenn.schoolDepartmentCenterDepartmental Papers (BE)
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