Departmental Papers (BE)

Document Type

Journal Article

Date of this Version

May 2000

Comments

Copyright 2000 IEEE. Reprinted from IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume 47, Issue 5, May 2000, pages 416-434.
Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=18224&puNumber=82

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Abstract

This paper discusses connectivity between neuromorphic chips, which use the timing of fixed-height fixed-width pulses to encode information. Address-events (log2 (N)-bit packets that uniquely identify one of N neurons) are used to transmit these pulses in real time on a random-access time-multiplexed communication channel. Activity is assumed to consist of neuronal ensembles--spikes clustered in space and in time. This paper quantifies tradeoffs faced in allocating bandwidth, granting access, and queuing, as well as throughput requirements, and concludes that an arbitered channel design is the best choice.The arbitered channel is implemented with a formal design methodology for asynchronous digital VLSI CMOS systems, after introducing the reader to this top-down synthesis technique. Following the evolution of three generations of designs, it is shown how the overhead of arbitrating, and encoding and decoding, can be reduced in area (from N to √N) by organizing neurons into rows and columns, and reduced in time (from log2 (N) to 2) by exploiting locality in the arbiter tree and in the row–column architecture, and clustered activity. Throughput is boosted by pipelining and by reading spikes in parallel. Simple techniques that reduce crosstalk in these mixed analog–digital systems are described.

Keywords

asynchronous logic synthesis, interchip communication, spiking neurons, virtual wiring

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Date Posted: 03 November 2004

This document has been peer reviewed.