Departmental Papers (ESE)


The paper describes a multichip analog parallel neural network whose architecture, neuron characteristics, synaptic connections, and time constants are modifiable. The system has several important features, such as time constants for time-domain computations, interchangeable chips allowing a modifiable gross architecture, and expandability to any arbitrary size. Such an approach allows the exploration of different network architectures for a wide range of applications, in particular dynamic real-world computations. Four different modules (neuron, synapse, time constant, and switch units) have been designed and fabricated in a 2µm CMOS technology. About 100 of these modules have been assembled in a fully functional prototype neural computer. An integrated software package for setting the network configuration and characteristics, and monitoring the neuron outputs has been developed as well. The performance of the individual modules as well as the overall system response for several applications have been tested successfully. Results of a network for real-time decomposition of acoustical patterns will be discussed.

Document Type

Journal Article

Date of this Version

January 1992


Copyright 1992 IEEE. Reprinted from IEEE Journal of Solid State Circuits, Volume 27, Issue 1, January 1992, pages 82-92.
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neural network, neuron, synapse, synaptic time constants, acoustical pattern analysis



Date Posted: 27 June 2007

This document has been peer reviewed.