A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter

Loading...
Thumbnail Image
Penn collection
Departmental Papers (ESE)
Degree type
Discipline
Subject
Electrical and Computer Engineering
Funder
Grant number
License
Copyright date
Distributor
Related resources
Author
Xu, Chao
Sargeant, Winslow
Contributor
Abstract

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.

Advisor
Date Range for Data Collection (Start Date)
Date Range for Data Collection (End Date)
Digital Object Identifier
Series name and number
Publication date
2003-07-01
Journal title
Volume number
Issue number
Publisher
Publisher DOI
Journal Issue
Comments
Postprint version. Published in Analog Integrated Circuits and Signal Processing, Volume 36, Issue 1-2, July 2003, pages 91-97. The original publication is available at www.springerlink.com. Publisher URL: http://dx.doi.org/10.1023/A:1024410016948
Recommended citation
Collection