An Axiomatic Memory Model for POWER Multiprocessors

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dc.contributor.authorMador-Haim, Sela
dc.contributor.authorMaranget, Luc
dc.contributor.authorSarkar, Susmit
dc.contributor.authorMemarian, Kayvan
dc.contributor.authorAlglave, Jade
dc.contributor.authorAlur, Rajeev
dc.contributor.authorOwens, Scott
dc.contributor.authorMartin, Milo
dc.contributor.authorSewell, Peter
dc.contributor.authorWilliams, Derek
dc.date2023-05-17T07:10:22.000
dc.date.accessioned2023-05-22T12:49:29Z
dc.date.available2023-05-22T12:49:29Z
dc.date.issued2012-07-01
dc.date.submitted2012-07-17T09:37:14-07:00
dc.description.abstractThe growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying their memory models formally and accurately, and in understanding and analyzing the behavior of concurrent software. This complexity is particularly evident in the IBM® Power Architecture® , for which a faithful specification was published only in 2011 using an operational style. In this paper we present an equivalent axiomatic specification, which is more abstract and concise. Although not officially sanctioned by the vendor, our results indicate that this axiomatic specification provides a reasonable basis for reasoning about current IBM® POWER® multiprocessors.We establish the equivalence of the axiomatic and operational specifications using both manual proof and extensive testing. To demonstrate that the constraint-based style of axiomatic specification is more amenable to computer-aided verification, we develop a SAT-based tool for evaluating possible outcomes of multi-threaded test programs, and we show that this tool is significantly more efficient than a tool based on an operational specification.
dc.description.commentsFrom the 24th International Conference, CAV 2012, Berkeley, CA, USA, July 7-13, 2012.
dc.identifier.urihttps://repository.upenn.edu/handle/20.500.14332/6616
dc.legacy.articleid1596
dc.legacy.fields10.1007/978-3-642-31424-7_36
dc.legacy.fulltexturlhttps://repository.upenn.edu/cgi/viewcontent.cgi?article=1596&context=cis_papers&unstamped=1
dc.rightsThe original publication is available at www.springerlink.com
dc.source.beginpage495
dc.source.endpage512
dc.source.issue559
dc.source.journalDepartmental Papers (CIS)
dc.source.journaltitleLecture Notes in Computer Science: Computer Aided Verification
dc.source.statuspublished
dc.source.volume7358
dc.subject.otherCPS Formal Methods
dc.subject.otherComputer Sciences
dc.titleAn Axiomatic Memory Model for POWER Multiprocessors
dc.typePresentation
digcom.contributor.authorMador-Haim, Sela
digcom.contributor.authorMaranget, Luc
digcom.contributor.authorSarkar, Susmit
digcom.contributor.authorMemarian, Kayvan
digcom.contributor.authorAlglave, Jade
digcom.contributor.authorOwens, Scott
digcom.contributor.authorisAuthorOfPublication|email:alur@cis.upenn.edu|institution:University of Pennsylvania|Alur, Rajeev
digcom.contributor.authorisAuthorOfPublication|email:milom@cis.upenn.edu|institution:University of Pennsylvania|Martin, Milo
digcom.contributor.authorSewell, Peter
digcom.contributor.authorWilliams, Derek
digcom.identifiercis_papers/559
digcom.identifier.contextkey3103124
digcom.identifier.submissionpathcis_papers/559
digcom.typeconference
dspace.entity.typePublication
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relation.isAuthorOfPublication77277168-ae34-46e9-b324-e3717ade5622
relation.isAuthorOfPublication0277bab3-1be2-4f99-9964-92e0ea36014e
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relation.isAuthorOfPublication.latestForDiscovery0277bab3-1be2-4f99-9964-92e0ea36014e
upenn.schoolDepartmentCenterDepartmental Papers (CIS)
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