A Shared-Memory Multiprocessor Implementation of Data-Parallel Operators for ML

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dc.contributor.authorSuciu, Dan
dc.contributor.authorHuelsbergen, Lorenz
dc.date2023-05-16T23:50:51.000
dc.date.accessioned2023-05-22T19:57:53Z
dc.date.available2023-05-22T19:57:53Z
dc.date.issued1994-12-01
dc.date.submitted2006-09-12T06:03:39-07:00
dc.description.abstractWe have designed and implemented an asynchronous data-parallel scheduler for the SML/NJ ML compiler. Using this general scheduler we built a data-parallel module that provides new operators to manipulate sequences (i.e., arrays, vectors) in parallel. Parallelization concerns such as thread creation and synchronization are hidden from the application programmer by ML's module abstraction. We find that languages with modules, higher-order functions and automatic parallel storage management can, in this manner, seamlessly support data-parallel operators. An implementation of applications using the new sequence module on an eight-processor shared-memory machine indicates that in some cases useful speedup is possible with our approach.
dc.description.commentsUniversity of Pennsylvania Institute for Research in Cognitive Science Technical Report No. IRCS-94-27.
dc.identifier.urihttps://repository.upenn.edu/handle/20.500.14332/37588
dc.legacy.articleid1172
dc.legacy.fulltexturlhttps://repository.upenn.edu/cgi/viewcontent.cgi?article=1172&context=ircs_reports&unstamped=1
dc.source.issue172
dc.source.journalIRCS Technical Reports Series
dc.source.statuspublished
dc.titleA Shared-Memory Multiprocessor Implementation of Data-Parallel Operators for ML
dc.typeReport
digcom.contributor.authorSuciu, Dan
digcom.contributor.authorHuelsbergen, Lorenz
digcom.identifierircs_reports/172
digcom.identifier.contextkey204459
digcom.identifier.submissionpathircs_reports/172
digcom.typereport
dspace.entity.typePublication
upenn.schoolDepartmentCenterIRCS Technical Reports Series
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