As photonic integration processes are becoming more advanced, many optical systems are now being in- tegrated on-chip, featuring portable and energy-efficient implementations with orders of magnitude reduction in cost and volume compared to their bench-top counterparts. The conventional thinking tends to treat pho- tonic integrated circuit (PIC)s like a unidirectional device. In this work, however, we are taking advantage of the low-latency and on-chip coherence properties provided by the PIC, in combination with the control and processing power readily available from a nearby electronic integrated circuit (EIC), to actively exploits the benefits and to address the known issues of the PIC through novel architectures and systems. In this work, three integrated electronic-assisted photonic systems with different application outlooks are presented. The presented systems leverage the low-latency, low-parasitic, and on-chip phase coherence of the PIC to address a few of the existing challenges through system-level electronic-photonic co-design. First, 40 Gb/s optical receiver for intensity modulation direct detection (IM/DD) optical links with a cost-effective packaging solution is presented. Since the wavelength of the electrical signals approaches the millimeter region, attention is given to the electromagnetic field distribution, packaging, signal integrity, and noise contributions. This receiver is enabled by the detailed noise analysis, careful modeling of both photonic and electronic devices, and a parasitic-aware design process. Second, a miniature laser wavelength stabilization system is demonstrated where the wavelength of a semiconductor laser (SCL) is locked to an RF frequency through a dispersive opto-electronic oscilla- tor (OEO). An order of magnitude reduction in the laser wavelength fluctuation is observed by engaging the prototyped system. This system maintains the laser wavelength without using another stable laser or an external optical cavity, which is useful for a compact realization of an optical frequency reference. Finally, the coherent receiver architectures with direct phase-locking and data-recovering are explored. Two architectures are presented. One is based on the feed-back approach and the other one is based on the feed-forward approach. The presented architectures extract the phase error in the error detecting branch first before compensating for the same error in the decoding branch after a small delay. The prototyped systems demonstrate the phase-locking and data-decoding with binary phase-shift keying (BPSK) and quadrature phase-shift keying (QPSK) modulated signals at 10 GBaud/s.