ScholarlyCommons

Title

On-the-Fly Programmable Hardware for Networks

Author(s)

Ilija Hadžić, University of Pennsylvania
Jonathan M. Smith, University of PennsylvaniaFollow

Document Type

Technical Report

Date of this Version

January 1998

Comments

University of Pennsylvania Department of Computer and Information Science Technical Report No. MS-CIS-98-04.

Abstract

Ongoing research in adaptive protocols and active networks has presumed that flexibility is offered exclusively through software systems, and the performance implications have generated considerable skepticism. The programmable Protocol Processing Pipeline (P4) exploits the dynamic reconfigurability of RAM based Field Programmable Gate Arrays (FPGAs) to provide both hardware performance and dynamic functionality to network components.

We use forward error correction (FEC) as an example of a protocol processing function. Our measurements show that P4 is able to process the data stream at OC-3 (155 Mbps) link rate, and consequently improve TCP performance in noisy environments.

Recommended Citation

Ilija Hadžić and Jonathan M. Smith, "On-the-Fly Programmable Hardware for Networks", . January 1998.