Timestamp Snooping: An Approach for Extending SMPs

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Sorin, Daniel J
Ailamaki, Anastassia
Alameldeen, Alaa R
Dickson, Ross M
Mauer, Carl J
Moore, Kevin E
Plakal, Manoj
Hill, Mark D
Wood, David A
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Abstract

Symmetric multiprocessor (SMP) servers provide superior performance for the commercial workloads that dominate the Internet. Our simulation results show that over one-third of cache misses by these applications result in cache-to-cache transfers, where the data is found in another processor’s cache rather than in memory. SMPs are optimized for this case by using snooping protocols that broadcast address transactions to all processors. Conversely, directory-based shared-memory systems must indirectly locate the owner and sharers through a directory, resulting in larger average miss latencies. This paper proposes timestamp snooping, a technique that allows SMPs to i) utilize high-speed switched interconnection networks and ii) exploit physical locality by delivering address transactions to processors and memories without regard to order. Traditional snooping requires physical ordering of transactions. Timestamp snooping works by processing address transactions in a logical order. Logical time is maintained by adding a few bits per address transaction and having network switches perform a handshake to ensure on-time delivery. Processors and memories then reorder transactions based on their timestamps to establish a total order. We evaluate timestamp snooping with commercial workloads on a 16-processor SPARC system using the Simics full-system simulator. We simulate both an indirect (butterfly) and a direct (torus) network design. For OLTP, DSS, web serving, web searching, and one scientific application, timestamp snooping with the butterfly network runs 6-28% faster than directories, at a cost of 13-43% more link traffic. Similarly, with the torus network, timestamp snooping runs 6-29% faster for 17-37% more link traffic. Thus, timestamp snooping is worth considering when buying more interconnect bandwidth is easier than reducing interconnect latency.

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2000-11-13
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Departmental Papers (CIS)
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2023-05-17T00:29:16.000
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Postprint version. Copyright ACM, 2000. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in Proceedings of the ninth international conference on Architectural support for programming languages and operating systems 2000, ASPLOS IX, Volume 28, Issue 5, November 2000, pages 25-36. Publisher URL: http://doi.acm.org/10.1145/378993.378998 NOTE: At the time of publication, author Milo Martin was affiliated with the University of Wisconsin-Madison. Currently (March 2007), he is a faculty member in the Department of Computer and Information Science at the University of Pennsylvania.
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