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An image sensor comprising an array of 128 by 50 super pixels, column parallel current conveyors and global difference double sampling (DDS) unit is presented. The super pixel consists of: a reset transistor, a readout transistor, four transfer transistors and four photodiodes. The photo pixel address switch is placed outside the pixel, effectively implementing 1.5 transistors per pixel using a sharing scheme of the readout and reset transistor. The column FPN of 0.43% from saturated level and SNR of 43.9 dB is measured. The total power consumption is 5 mW at 30 frame/s.
Gruev, V.; Yang, Z.; and Van der Spiegel, Jan, "Low-Power Reduced Transistor Image Sensor" (2009). Departmental Papers (ESE). Paper 581.
Date Posted: 22 December 2010
This document has been peer reviewed.