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In a macroscopic approach, a single-chip cortical patch is designed based on a the model of a bifurcating neuron. In this paper, the monolithic design of the bifurcating neuron is presented. The dynamic element is able to generate an arbitrary one-dimensional map with 12-bit resolution. The CMOS design employs a calibration scheme to maintain robustness against process variations. The element is fabrication in a 0.6um CMOS process, and it driven under signals with 1MHz frequency. It covers a die of 0.2 square mm, and consumes 40mW power, with a 5V supply.
cortical patch, bifurcating neuron, nonlinear element, one-dimensional logistic map
Jie Yuan, Nabil H. Farhat, and Jan Van der Spiegel, "A CMOS Monolithic Implementation of a Nonlinear Element for Arbitrary 1-D Map Generation", . May 2006.
Date Posted: 27 June 2007
This document has been peer reviewed.