Departmental Papers (ESE)

Document Type

Journal Article

Date of this Version

7-1-2003

Comments

Postprint version. Published in Analog Integrated Circuits and Signal Processing, Volume 36, Issue 1-2, July 2003, pages 91-97. The original publication is available at www.springerlink.com.
Publisher URL: http://dx.doi.org/10.1023/A:1024410016948

Abstract

A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.

 

Date Posted: 21 January 2006

This document has been peer reviewed.