Date of this Version
A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency.
Chao Xu, Winslow Sargeant, Kenneth R. Laker, and Jan Van der Spiegel, "A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter", . July 2003.
Date Posted: 21 January 2006
This document has been peer reviewed.