Departmental Papers (CIS)

Date of this Version

12-2013

Document Type

Conference Paper

Comments

IEEE Real-Time Systems Symposium (RTSS 2013), Vancouver, Canada, December 3-6, 2013.

An extended version of this paper is available at http://repository.upenn.edu/cis_papers/786/

Abstract

Multicore processors are becoming ubiquitous, and it is becoming increasingly common to run multiple real-time systems on a shared multicore platform. While this trend helps to reduce cost and to increase performance, it also makes it more challenging to achieve timing guarantees and functional isolation.

One approach to achieving functional isolation is to use virtualization. However, virtualization also introduces many challenges to the multicore timing analysis; for instance, the overhead due to cache misses becomes harder to predict, since it depends not only on the direct interference between tasks but also on the indirect interference between virtual processors and the tasks executing on them.

In this paper, we present a cache-aware compositional analysis technique that can be used to ensure timing guarantees of components scheduled on a multicore virtualization platform. Our technique improves on previous multicore compositional analyses by accounting for the cache-related overhead in the components’ interfaces, and it addresses the new virtualization-specific challenges in the overhead analysis. To demonstrate the utility of our technique, we report results from an extensive evaluation based on randomly generated workloads.

Subject Area

CPS Real-Time

Publication Source

34th IEEE Real-Time Systems Symposium (RTSS 2013)

Start Page

1

Last Page

10

DOI

10.1109/RTSS.2013.9

Copyright/Permission Statement

© 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.

Keywords

RT-Xen, cache-aware, compositional analysis, interface, multicore, real-time, virtualization

Bib Tex

@INPROCEEDINGS{6728856, author={Meng Xu and Phan, L.T.X. and Insup Lee and Sokolsky, O. and Sisu Xi and Chenyang Lu and Gill, C.}, booktitle={Real-Time Systems Symposium (RTSS), 2013 IEEE 34th}, title={Cache-Aware Compositional Analysis of Real-Time Multicore Virtualization Platforms}, year={2013}, month={Dec}, pages={1-10}, keywords={cache storage;cost reduction;multiprocessing systems;real-time systems;virtualisation;cache misses;cache-aware compositional analysis technique;cache-related overhead;cost reduction;functional isolation;indirect interference;multicore processors;multicore timing analysis;overhead analysis;real-time multicore virtualization platforms;real-time systems;shared multicore platform;virtual processors;Bandwidth;Computational modeling;Multicore processing;Program processors;Real-time systems;Timing;Virtualization;RT-Xen;cache-aware;compositional analysis;interface;multicore;real-time;virtualization}, doi={10.1109/RTSS.2013.9}, ISSN={1052-8725},}

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Date Posted: 18 February 2014

This document has been peer reviewed.