Date of this Version
Aditya Kanade, Rajeev Alur, Franjo Ivanċić, S. Ramesh, Sriram Sankaranarayanan, and K. C. Shashidhar, "Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models", Lecture Notes in Computer Science: Computer Aided Verification 5643, 430-445. June 2009. http://dx.doi.org/10.1007/978-3-642-02658-4_33
We present a methodology and a toolkit for improving simulation coverage of Simulink/Stateflow models of hybrid systems using symbolic analysis of simulation traces. We propose a novel instrumentation scheme that allows the simulation engine of Simulink/Stateflow to output, along with the concrete simulation trace, the symbolic transformers needed for our analysis. Given a simulation trace, along with the symbolic transformers, our analysis computes a set of initial states that would lead to traces with the same sequence of discrete components at each step of the simulation. Such an analysis relies critically on the use of convex polyhedra to represent sets of states. However, the exponential complexity of the polyhedral operations implies that the performance of the analysis would degrade rapidly with the increasing size of the model and the simulation traces. We propose a new representation, called the bounded vertex representation, which allows us to perform under-approximate computations while fixing the complexity of the representation a priori. Using this representation we achieve a trade-off between the complexity of the symbolic computation and the quality of the under-approximation. We demonstrate the benefits of our approach over existing simulation and verification methods with case studies.
CPS Formal Methods, CPS Model-Based Design
Lecture Notes in Computer Science: Computer Aided Verification
The original publication is available at www.springerlink.com
Date Posted: 16 July 2012