Departmental Papers (ESE)


A time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP's CMOS 1.2-µm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of < 35 ps, and a typical integral nonlinearity of < 200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~ 1 s range could be realized.

Document Type

Journal Article

Date of this Version

September 1994


Copyright 1994 IEEE. Reprinted from IEEE Journal of Solid State Circuits, Volume 29, Issue 9, September 1994, pages 1068-1076.
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time to charge converter, CAM, pipelining, associative memory



Date Posted: 27 June 2007

This document has been peer reviewed.