Departmental Papers (ESE)

Abstract

Complex spatio-temporal patterns can be clustered using a network of parametrically coupled logistic maps. This paper describes the processing element design of such a Cort-X system. Each Cort-X element consists of a non-linear coupling (LC) and a non-linear dynamic element (IRON). The circuits are designed for low-power operation and to be robust against process variations. This has been accomplished by using openloop circuits, and a self-calibration technique that compensate for process variations. The circuits were implemented in a 0.25 um, 2.5V CMOS process and consumes a total of 12mW of power at 1MHz which is about a factor of 20 less power than previous realizations. This opens the possibility for building a large-scale Cort-X system on a chip for the recognition of complex spatio-temporal patterns.

Document Type

Conference Paper

Date of this Version

May 2007

Comments

Copyright 2007 IEEE. Published in the Proceedings of the IEEE International Sympsium of Circuits and Systems (ISCAS), pp. 1017-1020, May 2007.

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Keywords

neural network, spatio-temporal pattern, logistic map, recognition, non-linear elements

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Date Posted: 26 June 2007

This document has been peer reviewed.