Technical Reports (CIS)

Document Type

Technical Report

Subject Area


Date of this Version

March 1988


University of Pennsylvania Department of Computer and Information Science Technical Report No. MS-CIS-88-19.


The Performance of a parallel algorithm depends in part on how the interconnection topology of the target parallel system matches the communication patterns of the algorithm. We describe how to generate a topology for a network that can be configured into and r-regular topology. The topology generated has small total expansion with respect to a given task graph. The expansion of an edge in a task graph is the length of the shortest path that the edge maps to in the processor graph. The algorithm used to generate the topologies is analyzed and its average case behavior is determined. In addition, this synthesis method is compared to the conventional approach of mapping a task graph onto a fixed processor topology.



Date Posted: 16 August 2007