Technical Reports (CIS)

Model Checking of Hierarchical State Machines

Rajeev Alur, University of Pennsylvania
Mihalis Yannakakis, Bell Laboratories

Document Type Technical Report

University of Pennsylvania Department of Computer and Information Science Technical Report No. MS-CIS-98-15.


Model checking is emerging as a practical tool for detecting logical errors in early stages of system design. We investigate the model checking of hierarchical (nested) systems, i.e. finite state machines whose states themselves can be other machines. This nesting ability is common in various software design methodologies and is available in several commercial modeling tools. The straightforward way to analyze a hierarchical machine is to flatten it (thus, incurring an exponential blow up) and apply a model checking tool on the resulting ordinary FSM. We show that this flattening can be avoided. We develop algorithms for verifying linear time requirements whose complexity is polynomial in the size of the hierarchical machine. We address also the verification of branching time requirements and provide efficient algorithms and matching lower bounds.


Date Posted: 22 May 2007