Departmental Papers (CIS)

Date of this Version

January 2008

Document Type

Journal Article

Comments

Copyright 2008 IEEE. Reprinted from IEEE Computer Architecture Letters, Volume 7, Issue 1, pages 9-12.

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Abstract

Several recently proposed techniques including CPR (Checkpoint Processing and Recovery) and NoSQ (No Store Queue) rely on reference counting to manage physical registers. However, the register reference counting mechanism itself has received surprisingly little attention. This paper fills this gap by describing potential register reference counting schemes for NoSQ, CPR, and a hypothetical NoSQ/CPR hybrid. Although previously described in terms of binary counters, we find that reference counts are actually more naturally represented as matrices. Binary representations can be used as an optimization in specific situations.

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Date Posted: 16 July 2008

This document has been peer reviewed.