Departmental Papers (CIS)

Date of this Version

February 2007

Document Type

Journal Article

Comments

Copyright 2007 IEEE. Reprinted from IEEE Micro, Volume 27, Issue 1, February 2007, pages 106-113.
Publisher URL: http://dx.doi.org/10.1109/MM.2007.17

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Abstract

The NoSQ microarchitecture performs store-load communication without a store queue and without executing stores in the out-of-order engine. It uses speculative memory bypassing for all in-flight store-load communication, enabled by a 99.8 percent accurate store-load communication predictor. The result is a simple, fast core data path containing no dedicated store-load forwarding structures.

Keywords

cisc, risc, vlwi architectures, microarchitecture, pipeline processors

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Date Posted: 26 July 2007

This document has been peer reviewed.