Departmental Papers (CIS)

Date of this Version

February 2007

Document Type

Journal Article


Copyright 2007 IEEE. Reprinted from IEEE Micro, Volume 27, Issue 1, February 2007, pages 106-113.
Publisher URL:

This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to By choosing to view this document, you agree to all provisions of the copyright laws protecting it.


The NoSQ microarchitecture performs store-load communication without a store queue and without executing stores in the out-of-order engine. It uses speculative memory bypassing for all in-flight store-load communication, enabled by a 99.8 percent accurate store-load communication predictor. The result is a simple, fast core data path containing no dedicated store-load forwarding structures.


cisc, risc, vlwi architectures, microarchitecture, pipeline processors



Date Posted: 26 July 2007

This document has been peer reviewed.