Date of this Version
A 1.2 V, 38 μW second-order ΔΣ modulator (ΔΣM) with a Signal Adaptive Control (SAC) architecture is fabricated in a 0.35 μm standard CMOS technology (Vt,n = 0.6V, Vt,p = -0.8V). This modulator achieves 75 dB dynamic range and 63 dB of peak SNDR at 6.8kHz Nyquist rate and an oversample ratio of 64. The proposed architecture effectively reduces the power dissipation while keeping the modulator performance almost unchanged.
delta-sigma converter, modulator, oversampling, adaptive architecture
Date Posted: 23 November 2004
This document has been peer reviewed.