Departmental Papers (ESE)

Document Type

Conference Paper

Date of this Version

March 2001

Comments

Copyright 2001 IEEE. Reprinted from Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits and Systems 2001 (DCAS 2001), pages P23-P26.
Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=19922

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Abstract

A 1.2 V, 38 μW second-order ΔΣ modulator (ΔΣM) with a Signal Adaptive Control (SAC) architecture is fabricated in a 0.35 μm standard CMOS technology (Vt,n = 0.6V, Vt,p = -0.8V). This modulator achieves 75 dB dynamic range and 63 dB of peak SNDR at 6.8kHz Nyquist rate and an oversample ratio of 64. The proposed architecture effectively reduces the power dissipation while keeping the modulator performance almost unchanged.

Keywords

delta-sigma converter, modulator, oversampling, adaptive architecture

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Date Posted: 23 November 2004

This document has been peer reviewed.