Departmental Papers (ESE)

Document Type

Conference Paper

Date of this Version

5-6-2001

Comments

Copyright 2001 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems 2001 (ISCAS 2001) Volume 1, pages 408-411.
Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=19933&page=6

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Abstract

This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework.

Keywords

background calibration, error correction, pipeline, analog--digital converter, ADC, LMS algorithm

 

Date Posted: 21 November 2004

This document has been peer reviewed.