Date of this Version
This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework.
background calibration, error correction, pipeline, analog--digital converter, ADC, LMS algorithm
Sonkusale, Sameer R.; Van der Spiegel, Jan; and Nagaraj, K., "Background Digital Error Correction Technique for Pipelined Analog-Digital Converters" (2001). Departmental Papers (ESE). Paper 53.
Date Posted: 21 November 2004
This document has been peer reviewed.