Departmental Papers (ESE)
Document Type
Conference Paper
Date of this Version
May 2001
Abstract
This paper describes a technique for digital error correction in pipelined analog-digital converters. It makes use of a slow, high resolution ADC in conjunction with an LMS algorithm to perform error correction in the background during normal conversion. The algorithm will be shown to correct for errors due to capacitor ratio mismatch, finite amplifier gain and charge injection within the same framework.
Keywords
background calibration, error correction, pipeline, analog--digital converter, ADC, LMS algorithm
COinS
Date Posted: 21 November 2004
This document has been peer reviewed.
Comments
Copyright 2001 IEEE. Reprinted from IEEE International Symposium on Circuits and Systems 2001 (ISCAS 2001) Volume 1, pages 408-411.
Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=19933&page=6
This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.