A CMOS Time to Digital Converter IC with 2 Level Analog CAM

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time to charge converter
CAM
pipelining
associative memory
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Gerds, Eric J.
Van Berg, Rick
Williams, Hugh H.
Callewaert, L.
Eyckmans, W.
Sansen, Willy
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A time to charge converter IC with an analog memory unit (TCCAMU) has been designed and fabricated in HP's CMOS 1.2-µm n-well process. The TCCAMU is an event driven system designed for front end data acquisition in high energy physics experiments. The chip includes a time to charge converter, analog Level 1 and Level 2 associative memories for input pipelining and data filtering, and an A/D converter. The intervals measured and digitized range from 8-24 ns. Testing of the fabricated chip resulted in an LSB width of 107 ps, a typical differential nonlinearity of < 35 ps, and a typical integral nonlinearity of < 200 ps. The average power dissipation is 8.28 mW per channel. By counting the reference clock, a time resolution of 107 ps over ~ 1 s range could be realized.

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1994-09-01
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Copyright 1994 IEEE. Reprinted from IEEE Journal of Solid State Circuits, Volume 29, Issue 9, September 1994, pages 1068-1076. Publisher URL: http://dx.doi.org/10.1109/4.309902 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
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