Departmental Papers (ESE)

Document Type

Conference Paper

Date of this Version

May 2006

Comments

Copyright 2006 IEEE. Reprinted from Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2006), May 2006, pages 4963-4966.

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Abstract

An architectural overview of an image sensor with general spatial processing capabilities on the focal plane is presented. The system has been fabricated on two separate tiers, implemented on silicon-on-insulator technology with vertical interconnect capabilities. One tier is dedicated to imaging, where photosensitivity and pixel fill have been optimized. The subsequent layers contain noise suppression and digitally controlled analog processing elements, where general spatial filtering is computed. The digitally controlled aspect of the processing unit allows generic receptive fields to be computed on read out. The image is convolved with four receptive fields in parallel. The chip provides parallel readout of the filtered results and the intensity image.

Keywords

3-D technology, focal plane imager

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Date Posted: 27 June 2007

This document has been peer reviewed.