Analog Realization of Arbitrary One-Dimensional Maps

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Bifurcating neuron (BN)
coupled map lattice
neural network
one-dimensional (1-D) map
parametrically coupled map lattice (PCML)
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Del Moral Hernandez, Emilio
Lee, Geehyuk
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An increasing number of applications of a one-dimensional (1-D) map as an information processing element are found in the literature on artificial neural networks, image processing systems, and secure communication systems. In search of an efficient hardware implementation of a 1-D map, we discovered that the bifurcating neuron (BN), which was introduced elsewhere as a mathematical model of a biological neuron under the influence of an external sinusoidal signal, could provide a compact solution. The original work on the BN indicated that its firing time sequence, when it was subject to a sinusoidal driving signal, was related to the sine-circle map, suggesting that the BN can compute the sine-circle map. Despite its rich array of dynamical properties, the mathematical description of the BN is simple enough to lend itself to a compact circuit implementation. In this paper, we generalize the original work and show that the computational power of the BN can be extended to compute an arbitrary 1-D map. Also, we describe two possible circuit models of the BN: the programmable unijunction transistor oscillator neuron, which was introduced in the original work as a circuit model of the BN, and the integrated-circuit relaxation oscillator neuron (IRON), which was developed for more precise modeling of the BN. To demonstrate the computational power of the BN, we use the IRON to generate the bifurcation diagrams of the sine-circle map, the logistic map, as well as the tent map, and then compare them with exact numerical versions. The programming of the BN to compute an arbitrary map can be done simply by changing the waveform of the driving signal, which is given to the BN externally; this feature makes the circuit models of the BN especially useful in the circuit implementation of a network of 1-D maps.

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2003-12-01
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Copyright 2003 IEEE. Reprinted from IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Volume 50, Issue 12, December 2003, pages 1538-1547. Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=28126&puNumber=81 This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.
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