Departmental Papers (BE)

Document Type

Journal Article

Date of this Version

July 2004

Comments

Copyright 2004 IEEE. Reprinted from IEEE Transactions on Circuits and Systems--I: Regular Papers, Volume 51, Issue 7, July 2004, pages 1292-1300.
Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=29094&puNumber=8919

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Abstract

We present results for a scalable multiple-access inter-chip link that communicates binary activity between two-dimensional arrays fabricated in deep submicrometer CMOS. Capacity scales with integration density because an entire row is read and written in parallel. Row activity is encoded in a burst: The row address followed by a column address for each active cell. We predict the distribution of burst lengths when transmission is initiated by active cells and access is arbitered using a two-level queuing model. Agreement with the experiment is excellent for loads over 50% but not for lighter loads, where our assumption that service time is exponentially distributed breaks down. We also quantify the throughput–latency tradeoff. The price of an n-fold increase in throughput is an n per Ncol timing error in a cell’s inter-event interval, where Ncol is the number of cells per row. Links implemented in 0.6, 0.4, and 0.25 micrometer are compared; the highest burst-rate achieved was 27.8 M events/s.

Keywords

asynchronous logic synthesis, event-driven communication, fair arbiter design, neuromorphic systems, parallel readout, pixel-level quantization

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Date Posted: 28 October 2004

This document has been peer reviewed.