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This paper describes an address event representation (AER) transceiver chip that accepts 2D images and produces 2D output images equal to the input filtered by even and odd symmetric orientation selective spatial filters. Both input and output are encoded as spike trains using a differential ON/OFF representation, conserving energy and AER bandwidth. The spatial filtering is performed by symmetric analog circuits that operate on input currents obtained by integrating the input spike trains, and which preserve the ON/OFF representation. This chip is a key component of a multi-chip system we are constructing that is inspired by the visual cortex. We present measured results from a 32 x 64 pixel prototype, which was fabricated in the TSMC0.25 μm process on a 3.84mm by 2.54mm die. Quiescent power dissipation was 3mW.
Date Posted: 10 November 2004
This document has been peer reviewed.