Departmental Papers (BE)

Document Type

Journal Article

Date of this Version

April 2004

Abstract

Seeking to match the brain’s computational efficiency [14], we draw inspiration from its neural circuits. To model the four main output (ganglion) cell types found in the retina, we morphed outer and inner retina circuits into a 96 x 60-photoreceptor, 3.5 x 3.3 mm2, 0.35 μm-CMOS chip. Our retinomorphic chip produces spike trains for 3600 ganglion cells (GCs), and consumes 62.7 mW at 45 spikes/s/GC. This chip, which is the first silicon retina to successfully model inner retina circuitry, approaches the spatial density of the retina. We present experimental measurements showing that the chip’s subthreshold current-mode circuits realize luminance adaptation, bandpass spatiotemporal filtering, temporal adaptation and contrast gain control. The four different GC outputs produced by our chip encode light onset or offset in a sustained or transient fashion, producing a quadrature-like representation. The retinomorphic chip’s circuit design is described in a companion paper [Zaghloul and Boahen (2004)].

Comments

Copyright 2004 IEEE. Reprinted from IEEE Transactions on Biomedical Engineering, Volume 51, Issue 4, April 2004, pages 667-675.
Publisher URL: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isNumber=28546&puNumber=10

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Keywords

adaptive circuits, neural systems, neuromorphic engineering, prosthetics, vision

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Date Posted: 09 November 2004

This document has been peer reviewed.